A circuit model for defective bilayer graphene transistors

This paper investigates the behaviour of a defective single-gate bilayer graphene transistor. Point defects were introduced into pristine graphene crystal structure using a tightly focused helium ion beam. The transfer characteristics of the exposed transistors were measured ex-situ for different defect concentrations. The channel peak resistance increased with increasing defect concentration whilst the on–off ratio showed a decreasing trend for both electrons and holes. To understand the electrical behaviour of the transistors, a circuit model for bilayer graphene is developed which shows a very good agreement when validated against experimental data. The model allowed parameter extraction of bilayer transistor and can be implemented in circuit level simulators.<br/

Using event-B and Modelica to evaluate thermal management strategies in many core systems

Dynamic thermal management is an increasingly critical and complex part of the run-time management of manycore systems. Methods of controlling temperature include thread migration, dynamic voltage and frequency scaling and power gating using various strategies and combinations of each. In the PRiME project we are developing run-time management systems to sustain the scaling of many-core systems. As part of this development we are investigating the relative benefits of different thermal management strategies by co-simulating a Modellica model of the characteristics of a many-core device with a discrete Event-B model of the run-time manager. The results enable us to efficiently design more elaborate experiments on real hardware platforms in order to validate the run time management

Susceptible workload driven selective fault tolerance using a probabilistic fault model

In this paper, we present a novel fault tolerance design technique, which is applicable at the register transfer level, based on protecting the functionality of logic circuits using a probabilistic fault model. The proposed technique selects the most susceptible workload of combinational circuits to protect against probabilistic faults. The workload susceptibility is ranked as the likelihood of any fault to bypass the inherent logical masking of the circuit and propagate an erroneous response to its outputs, when that workload is executed. The workload protection is achieved through a Triple Modular Redundancy (TMR) scheme by using the patterns that have been evaluated as most susceptible. We apply the proposed technique on LGSynth91 and ISCAS85 benchmarks and evaluate its fault tolerance capabilities against errors induced by permanent faults and soft errors. We show that the proposed technique, when it is applied to protect only the 32 most susceptible patterns, achieves on average of all the examined benchmarks, an error coverage improvement of 98% and 94% against errors induced by single stuck-at faults (permanent faults) and soft errors (transient faults), respectively, compared to a reduced TMR scheme that protects the same number of susceptible patterns without ranking them

Optimum stochastic modeling for GNSS tropospheric delay estimation in real-time

In GNSS data processing, the station height, receiver clock and tropospheric delay (ZTD) are highly correlated to each other. Although the zenith hydrostatic delay of the troposphere can be provided with sufficient accuracy, zenith wet delay (ZWD) has to be estimated, which is usually done in a random walk process. Since ZWD temporal variation depends on the water vapor content in the atmosphere, it seems to be reasonable that ZWD constraints in GNSS processing should be geographically and/or time dependent. We propose to take benefit from numerical weather prediction models to define optimum random walk process noise. In the first approach, we used archived VMF1-G data to calculate a grid of yearly and monthly means of the difference of ZWD between two consecutive epochs divided by the root square of the time lapsed, which can be considered as a random walk process noise. Alternatively, we used the Global Forecast System model from National Centres for Environmental Prediction to calculate random walk process noise dynamically in real-time. We performed two representative experimental campaigns with 20 globally distributed International GNSS Service (IGS) stations and compared real-time ZTD estimates with the official ZTD product from the IGS. With both our approaches, we obtained an improvement of up to 10% in accuracy of the ZTD estimates compared to any uniformly fixed random walk process noise applied for all stations

A dedicated bit-serial hardware neuron for massively-parallel neural networks in fast epilepsy diagnosis

This paper outlines the feasibility of detecting epilepsy though low-cost and low-energy dedicated hardware with bit-serial processing. The concept of a novel bit-serial data processing unit (DPU) is presented which implements the functionality of a complete neuron. The proposed approach has been tested using various network configurations and compared with related work. The proposed DPU uses only 24 Adaptive Logic Modules on an Altera Cyclone V FPGA. An array of these DPUs are controlled by a simple finite state machine. The proposed DPU allows the construction of complex hardware ANNs that can be implemented in portable equipment that suits the needs of a single epileptic patient in his or her daily activities to detect impending seizure events

Weighting of Multi-GNSS Observations in Real-Time Precise Point Positioning

The combination of Global Navigation Satellite Systems (GNSS) may improve the accuracy and precision of estimated coordinates, as well as the convergence time of Precise Point Positioning (PPP) solutions. The key conditions are the correct functional model and the proper weighting of observations, for which different characteristics of multi-GNSS signals should be taken into account. In post-processing applications, the optimum stochastic model can be obtained through the analysis of post-fit residuals, but for real-time applications the stochastic model has to be defined in advanced. We propose five different weighting schemes for the GPS + GLONASS + Galileo + BeiDou combination, including two schemes with no intra-system differences, and three schemes that are based on signal noise and/or quality of satellite orbits. We perform GPS-only and five multi-GNSS solutions representing each weighting scheme. We analyze formal errors of coordinates, coordinate repeatability, and solution convergence time. We found that improper or equal weighting may improve formal errors but decreases coordinate repeatability when compared to the GPS-only solution. Intra-system weighting based on satellite orbit quality allows for a reduction of formal errors by 40%, for shortening convergence time by 40% and 47% for horizontal and vertical components, respectively, as well as for improving coordinate repeatability by 6%

A dual-gate graphene FET model for circuit simulation - SPICE implementation

This paper presents a SPICE compatible model of a dual-gate bilayer graphene field effect transistor (GFET). The model describes the functionality of the transistor in all the regions of operation for both hole and electron conduction. We present closed form analytical equations that define the boundary points between the regions to ensure Jacobian continuity for efficient circuit simulator implementation. A saturation displacement current is proposed to model the drain current when the channel becomes ambipolar. The model proposes a quantum capacitance that varies with the surface potential. The model has been implemented in Berkeley SPICE-3 and it shows a good agreement against experimental data with the NRMS error less than 10%<br/

Tamper resistant design of convolutional neural network hardware accelerator

The globalisation of supply chains and manufacturing processes can lead to loss of control over the manufacturing process and exposure to potentially malicious third parties, thus making the security of Convolutional Neural Network hardware accelerators compromised by emerging attacks (e.g., hardware Trojan(HT) insertion attacks and backdoor attacks from third-party dataset providers). In this paper, a new defence mechanism, called Shuffle and Substitution-Based Defence Mechanism(SSDM), is proposed to effectively defend against attacks launched by attackers from the third-party dataset providers and the Fabrication phase. The new countermeasure proposed in this paper can not only effectively suppress the activation of most existing HTs, but also greatly increase the difficulty for adversaries from third-party dataset providers to successfully execute backdoor attacks. The experimental results show that the new defensive countermeasures are effective in preventing HTs from being activated and significantly increasing the difficulty of backdoor attacks

Low cost error monitoring for improved maintainability of IoT applications

Electronic systems with power-constrained embedded devices are used for a variety of IoT applications, such as geomonitoring, parking sensors and surveillance. Such applications may tolerate few errors. However, with the increasing occurrence of faults in-the-field, devices that exhibit systematic erroneous behaviour must be eventually identified and replaced. In this paper, we propose a novel low cost error monitoring technique to assist the maintainability planning of low power IoT applications by ranking devices based on the systematic erroneous behaviour they exhibit. Small on-chip monitors are used to collect the signal probability information at the outputs of each device which is then transmitted to the system software via the communications channel of the system to rank them accordingly. To evaluate the error monitoring capabilities of the proposed technique, we injected multiple bit-flips and stuck-at faults on a set of the EPFL and the ISCAS benchmarks. Results demonstrate an average error coverage of 84.4% and 73.1% of errors induced by bit-flips and stuck-at faults, respectively, with an average area cost of 1.52%. A maintainability planning simulation shows that the proposed technique achieves a reduction of 26x to 263x in area cost and static power, and consumes over 625x less power for communications when compared against duplication and comparison